A DRAM (dynamic random access memory) is a representative device of a semiconductor memory device, in which one transistor and one capacitor forms a memory cell. The memory cell of the DRAM requires refresh for a retention operation of data. As the DRAM has a high density, a cell size is reduced and operating current is gradually reduced. Thus, stable data retention operation is more and more important.
The capacitor constituting the memory cell of the DRAM is a storage capacitor for storing data. The storage capacitor includes a storage electrode for storing data and a cell plate electrode for increasing data retention time. Typically, cell plate voltage VCP generated at a level corresponding to about ½ of core voltage VCORE is supplied to the cell plate electrode. The voltage VCP generated at the level corresponding to about ½ of the core voltage VCORE is also used as bit line precharge voltage VBLP to provide criterion for signal detection.
An internal voltage generating circuit, which generates voltage used as cell plate voltage VCP and bit line precharge voltage VBLP, must generate internal voltage stably driven regardless of temperature variation. Since the internal voltage generating circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors, driving force for generating the internal voltage is changed as temperature changes. Referring to Table 1 below, as the temperature changes, variation of threshold voltage of a PMOS transistor is greater than that of an NMOS transistor. Further, as the threshold voltage changes, variation of current driving force of an NMOS transistor is greater than that of a PMOS transistor. Thus, the level of the internal voltage generated through PMOS and NMOS transistors is changed as temperature changes.
TABLE 1Type−40° C.25° C.90° C.NMOSVTE (V)0.5310.4770.430typeIdsat (A)4.3303.9793.704PMOSVTE (V)0.7990.6300.467typeIdsat (A)1.2201.3811.513